The present invention relates to a method and a test device for detecting addressing errors in control units.
For safety reasons, control units for motor vehicles and, in particular, for braking systems and systems controlling the dynamics of the vehicle movement, such as ABS, ASR, ESP and similar systems, have a redundant construction with two microprocessors which monitor one another.
For reasons of cost, however, control units are also applied which use only one microprocessor.
An important monitoring operation consists of testing whether certain memory cells can be written to and read.
In practice, so-called addressing errors also occur; that is, during a writing operation onto a certain memory cell, a different cell is unintentionally inscribed. It may occur in this case that only the wrong, that is, the non-addressed cell is inscribed, or that the addressed as well as a non-addressed cell are inscribed. Specifically, the latter error cannot be detected by means of conventional test devices.
It is therefore an object of the invention to further develop a method and a test device of the above-mentioned type such that any addressing errors are also detected in a perfect manner.
This object is achieved by a method and test device for detecting addressing errors in control units, wherein test data preset when the control unit is switched off by the user are written into all addressable memory cells, and are subsequently read out again and are compared with the test data. Advantageous embodiments and further developments are described and claimed herein.
It is the basic principle of the invention to write test data, which are preset when the control unit is switched off by the user, into all addressable memory areas, to subsequently read them out again, and to compare them with the test data.
The preset test data are preferably defined such that different test data are available for each addressable area.
According to a further development of the invention, several different test data are written into the addressable memory cells and are read out again in a successive manner with respect to time. According to another further development of the invention, the test data are preset such that a certain byte of an address, preferably the low byte, is written into the memory cell of this preset address.
According to another further development of the invention, the results of the comparison are stored and, if an error is detected, it is signalled to the user when the control unit is switched back on.
In the following, the invention will be explained in greater detail by means of an embodiment in connection with the drawing.